Low-Power Op-Amp

For my Analog Design class, each student was tasked with designing an OpAmp in 0.5um technology with the following specifications:

Open-loop gain of at least 3000 V/V
Unity-gain Bandwidth of at least 20 MHz
Phase Margin of at least 50°
Slew-rate of at least 3 V/us
Output voltage swing within 500mV of each rail
ICMR that include one of the rails
PSRR of -60dB at 60Hz and -40dB at 1 MHz

In addition, each student had to select an optional specification. I chose low quiescent power whose specification was to be below 200 uW. Each spec had to be run over corners which varied the supply voltages, MOSFET process, and temperature. In all there were 45 different corners. My final paper can be found here. The physical layout was just a quick overview of the floorplan and not a final design. Overall, the opamp performed fairly well. The only spec that I completely missed was the unity-gain bandwidth (as the compliance table below shows). This is due to the nature of the architecture in that by using a Folded-Cascode, I decrease the pole location with a decrease in current (since the output impedance is inversely related to current). Since I needed a low-quiescent design and couldn’t quite get any dynamic biasing scheme working, I had to keep the current very low to achieve a balance between power, gain, and phase margin. This required me to sacrifice bandwidth, unfortunately. Other than that, any other spec I missed was just by a small margin and could easily be rectified with a bit more tuning. Eventually I just got to the point where I needed to stop tuning and start recording results (since it is quite time consuming to fiddle with a parameter, run corners simulation, and analyze results over and over again). I was happy with what my amplifier produced so I stuck with it. Below are various plot corresponding to each spec.

Opamp Architecture

Open Loop Gain and Bandwidth

Open Loop Phase Margin

Power Consumption

PSRR on VCC

PSRR on VSS

Slew Rate

Large Signal Voltage Swing