Kevin Fronczak
Analog Circuit Designer


Analog circuit designer with experience implementing low-noise and low-power sensor designs.

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Staff Mixed Signal IC Design Engineer at Sony Electronics in Rochester, NY from July 2018 to Present

  • Involved in the power management architecture for next generaon ultra low power image sensors, including the design of a sub-uW LDO capable of supporng loads 1000x the quiescent current

  • Responsible for the design of circuits to interface with a pixel array on a low-power CMOS imaging product. This work also involved generating detailed pixel models for simulations, as well as the study of power and area reduction techniques to improve product marketability and cost.

Sr. Mixed Signal IC Design Engineer at Synaptics Inc in Rochester, NY from Feb 2014 to July 2018

Fingerprint Sensing

  • Designed a small area, noise-optimized current-mode front-end which helped reduce die cost by nearly 50%
  • Designed an innovative multi-level mixing topology to improve SNR
  • Drove circuit and system implementation of a small area current-mode front-end in order to prove ability of the new technology to sense a fingerprint (stepping-stone for fingerprint sensor cost reduction)
  • Led efforts to evaluate, track, and debug new silicon for any potential issues that could require a metal or all-layer revision, allowing for efficient evaluation of benefits/risks of a potential spin
  • Designed a capacitive background cancellation circuit with sub-femtofarad resolution

Touch Sensing

  • Designed a small-area current-mode baseline correction circuit for TDDI (Touch and Display Driver IC) in order to reduce die cost and maintain competitive edge in TDDI market
  • Designed switched capacitor demodulator and sample-and-hold circuitry for TDDI analog front-ends

Low Power and Reference Circuits

  • Architected and led the implementation of an experimental small area, nano-Amp reference architecture (current mirrors, oscillators, etc) with the goal of reducing standby power without sacrificing performance
  • Designed a sub 1-V bandgap reference with innovative base-cancellation circuit for TDDI chips
  • Aided in development of a top-level mixed-signal verification flow for capacitive fingerprint sensors, allowing teams to efficiently catch system-level bugs before tapeout

Display Drivers

  • Experience with MIPI DSI from transistor-level design through top-level verification and production test
  • Experience designing high-voltage gate-line drivers


  • Experience working closely and effectively with multidisciplinary teams to ensure smooth silicon design and bring-up all the way through to production
  • Have designed circuits in 130nm and 55nm technologies
  • Very familiar and comfortable with Cadence design flow for IC design
  • Experience using MATLAB for both system design and for testing of ASICs
  • Focus on fundamental understanding of circuits for architectural comparisons is a strength (i.e. pencil-and-paper analysis)
  • Attended a week-long Continuous-Time Delta Sigma Converter course held by MEAD (taught by Drs. Pavan, Schreier, and Hanumolu).

Silicon Validation Contractor at Synaptics Inc in Rochester, NY from Jun 2013 to Feb 2014

  • Performed extensive validation on LDOs, VCOM drivers, LCD level shifters, and high-speed MIPI D-PHY architecture

Analog Design Co-op at Intel Corporation in Hudson, MA from Mar 2012 to Aug 2012

  • Implemented a tool to extract on-chip decoupling capacitors to minimize off-chip capacitor size
  • Implemented a tool to rapidly compare pad layout revisions to minimize errors due to manual inspection


Rochester Institute of Technology in Rochester, NY from Sep 2008 to Aug 2013
Master of Science and Bachelor of Science in Electrical Engineering with a graduate GPA of 4.0

Thesis: Stability Analysis of Switched DC-DC Boost Converters for Integrated Circuits

  • Investigated small-signal modeling and stability requirements for boost converters, as well as a variety of OTA-based controller topologies, in order to aid in the design and measurement of boost converter stability on an ASIC. Also investigated use of genetic algorithms as a way to optimize controller design.


  • US 9,780,736 - Temperature compensated offset cancellation for high-speed amplifiers - Grant Oct. 3, 2017
  • US 9,817,428 - Current-mode Bandgap Reference with Proportional to Absolute Temperature Current and Zero Temperature Current -Generation - Grant Nov. 14, 2017
  • US 10,394,386 - Interference Detection - Grant Aug. 27, 2019
  • US 15/685,937 - Mixer Circuit - Application February 28, 2019
  • US 15/885,769 - Oscillator Temperature Coefficient Adjustment - Pending Jan. 31, 2018