In the Fall 2015 edition of “IEEE Solid-State Circuits Magazine”, Sansen published the following flowchart, illustrating a design flow using the inversion coefficient where the designer only needs to make two choices: the actual inversion coefficient, and the length of the device . All other parameters will fall out of the equations.
Let’s do a little exercise to see this methodology work. Say we are asked to design a simple 5T OTA with a required DC Gain of 40dB, GBW of 100 MHz and a load capacitance of 1 pF.
So our final list of design parameters for the input pair of our 5T OTA is:
I went ahead and put a schematic in cadence using a PDK I have access to and got the following result using stability analysis. We hit our desired 40dB gain target and are quite close to the GBW requirement of 100 MHz (it turns out, the trans-conductance is a bit low in the simulation due to a mismatch between the actual transistor and what we used as an approximation).
Instead of haphazardly choosing the inversion coefficient, we could also sweep this value to try and find an optimum point for our application. Below is a plot of the drain current and width-to-length ratio versus a sweep of the inversion coefficient. Using a plot like this would allow for an optimization of area and power given the GBW and load capacitance requirements.
Hopefully I’ve shown the power of using the inversion coefficient as a basis for design. Being able to quickly, and intelligently, optimize for power/speed/noise/area/etc. is extremely important and the inversion coefficient method that Sansen presented in the forum at ISSCC this year is quite ideal for this.
 Enz et. al, “An Analytical MOS Transistor Model Valid in all Regions of Operation and Dedicated to Low Voltage and Low Current Applications”, in Analog Integrated Circuits and Signal Processing, 1995.
 Sansen, “Analog Design Essentials”, Springer 2006.
 Cunha et. al, “A MOS Transistor Model For Analog Circuit Design”, in Journal of Solid State Circuits, 1998.  Sansen, “Minimum Power in Analog Amplifying Blocks”, in IEEE Solid-State Circuits Magazine, 2015 (vol. 7, issue 4)